1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly relates to an internal voltage generation circuit capable of adjusting internal voltage during a test.
2. Description of the Background Art
Generally, periods in which failures occur to a semiconductor memory device are roughly divided into three periods, which periods are also referred to as a an initial failure period, a chance failure period and a wear-out failure period in the order of time.
In the initial failure period, a defect at the time of the manufacture of a semiconductor memory device appears as a failure. The initial failure period is a period in which an initial failure occurs right after starting the use of the semiconductor. The rate of this initial failure sharply decreases with the passage of time. The initial failure period is followed by the chance failure period in which a low failure rate continuous for a certain period of time. With time, the life of the semiconductor memory device nears the useful life thereof and the semiconductor memory device enters the wear-out failure period in which the failure rate suddenly increases. If the operation reliability of the semiconductor memory device while being in use is considered, it is necessary to use the semiconductor memory device within the chance failure period. Namely, it is necessary to remove semiconductor memories to which initial failures occur before shipment. To this end, semiconductor memories are subjected to accelerated operation aging for a certain period of time and to screening for removing defects having initial failures.
To perform efficient screening, it is necessary to discover an initial failure in short time. Generally, a screening method for raising internal voltage which is used as operating power supply voltage in semiconductor memory device from voltage in normal operation, applying high field stress to the memory and thereby screening semiconductor memories is used.
FIG. 8 is a conceptual view of a conventional internal voltage generation circuit 20 which generates internal voltage applied to the internal circuit of a semiconductor memory device.
Referring to FIG. 8, internal voltage generation circuit 20 includes reference voltage generation circuits 300a to 300c which generate reference voltages REF1 to REF3, respectively, and internal voltage generation units 400a to 400c which receive corresponding to reference voltages REF1 to REF3, and generate internal voltages V1 to V3 respectively.
FIG. 9 is a circuit block diagram of reference voltage generation circuit 300a generating reference voltage REF1. Since reference voltage generation circuits 300a to 300c are equal in configuration, the configuration of reference voltage generation circuit 300a will be typically explained herein.
Referring to FIG. 9, reference voltage generation circuit 300a includes a current mirror amplifier 310, a starting circuit 320 which operates at startup, a constant current circuit 330 which generates a constant current, a tuning circuit 340 and a reference voltage setting circuit 350.
Reference voltage setting circuit 350 sets the voltage level of an internal node to be described later. Current mirror amplifier 310 generates a reference voltage in accordance with the voltage level of this internal node. Tuning circuit 340 and constant current circuit 330 are used to adjust the voltage level of the internal node. Constant current circuit 330 supplies a constant current to reference voltage setting circuit 350, and tuning circuit 340 adjusts a resistance element to be described later and tunes the voltage level of the internal node. Starting circuit 320 indicates the activation of constant current circuit 330 when the power of the semiconductor memory device is turned on.
Current mirror amplifier 310 includes P-channel MOS transistors 311 and 312, and N-channel MOS transistors 313 to 315. P-channel MOS transistor 311 and N-channel MOS transistor 313 are connected in series between a power supply voltage VCC and a node N1 through a node N2 and the gates of P-channel MOS transistors 311 and N-channel MOS transistor 313 are connected to node N2 and an internal node N6, respectively. P-channel MOS transistor 312 and N-channel MOS transistor 314 are connected in series between power supply voltage VCC and node N1 through a node N0 and the gates of P-channel MOS transistors 312 and N-channel MOS transistor 314 are connected to node N2 and node N0, respectively. Further, N-channel MOS transistor 315 is connected between node N1 and a ground voltage GND and the gate thereof is connected to a node N4.
By such a current mirror structure, current mirror amplifier 310 sets reference voltage REF1 generated at node N0 at the voltage level of voltage Vn6 of internal node N6 connected to the gate of N-channel MOS transistor 313.
Starting circuit 320 includes a P-channel MOS transistor 321 and an N-channel MOS transistor 322.
P-channel MOS transistors 321 and N-channel MOS transistor 322 are connected between power supply voltage VCC and ground voltage GND through a node N3 and the gates of P-channel MOS transistors 321 and N-channel MOS transistor 322 are connected to ground voltage GND and a node N4, respectively.
At startup, starting circuit 320 raises the voltage level of node N3 in response to the rise of power supply voltage VCC. Following this, an N-channel MOS transistor 323 which is provided in constant current circuit 330 becomes conductive, nodes N4 and N5 are electrically connected to each other and constant current circuit 330 is activated. It is noted that starting circuit 320 turns N-channel MOS transistor 323 into a nonconductive state after the passage of a predetermined period. This is because the voltage level of node N3 decreases if N-channel MOS transistor 322 is conductive.
Constant current circuit 330 includes a resistance 332, P-channel MOS transistors 331 and 333, and N-channel MOS transistors 323, 334 and 335.
P-channel MOS transistors 331 and N-channel MOS transistor 334 are connected in series between power supply voltage VCC and ground voltage GND through node N5 and the gates of P-channel MOS transistors 331 and N-channel MOS transistor 334 are connected to nodes N5 and N4, respectively. Resistance 332, P-channel MOS transistors 333 and N-channel MOS transistor 335 are connected in series between power supply voltage VCC and ground voltage GND through node N4 and the gates of P-channel MOS transistors 333 and N-channel MOS transistor 335 are connected to nodes N5 and N4, respectively.
N-channel MOS transistor 323 is connected between nodes N4 and N5 and the gate thereof is connected to node N3. N-channel MOS transistors 334 and 335 constitute a current mirror circuit. If N-channel MOS transistors 334 and 335 have high channel resistances, the same current is carried to P-channel MOS transistors 331 and 333 by N-channel MOS transistors 334 and 335 which constitute a current mirror circuit.
Reference voltage setting circuit 350 includes P-channel MOS transistors 302 and 351 to 361, and an inverter 362.
P-channel MOS transistor 302 is connected between power supply voltage VCC and internal node N6 and the gate thereof is connected to node N5. P-channel MOS transistors 351 to 357 are connected in series between internal node N6 and ground voltage GND and the gates thereof are connected to ground voltage GND. P-channel MOS transistors 358 to 361 are provided as transistor switches so as to short-circuit P-channel MOS transistors 352 to 355, respectively (which P-channel MOS transistors 358 to 361 will be also referred to as xe2x80x9ctransistor switchesxe2x80x9d hereinafter), and the gates thereof receive the input of tuning circuit 340. The gate of P-channel MOS transistor 361 receives a signal input inverted from the output signal of tuning circuit 340 by inverter 362.
P-channel MOS transistor 302 has the same size (same ratio of channel width to channel length) as that of P-channel MOS transistor 331. A constant current Ict which is the same in magnitude as a current carried to P-channel MOS transistor 331, is carried to this P-channel MOS transistor 302.
The channel resistances of P-channel MOS transistors 351 to 357 causes voltage drop due to their resistance components. It is assumed herein that the channel resistances of P-channel MOS transistors 358 to 361 are sufficiently lower than those of P-channel MOS transistors 351 to 357.
Therefore, if a combined channel resistance of P-channel MOS transistors 351 to 357 is assumed as Rc, a constant voltage Vn6 generated at internal node N6 is expressed by the following equation.
Vn6=Rcxc2x7Ict.
Accordingly, constant voltage Vn6 can be adjusted by selectively setting transistor switches 358 to 361 and changing combined channel resistance Rc. As already described, the conductive states of P-channel MOS transistors 358 to 361 can be selectively set by tuning circuit 340.
FIG. 10 is a circuit block diagram of tuning circuit 340.
Referring to FIG. 10, tuning circuit 340 includes tuning units 344a to 344d which are provided to correspond to P-channel MOS transistors 358 to 361, respectively.
Since tuning units 344a to 344d are equal in configuration, tuning unit 344a will be typically described herein.
Tuning unit 344a includes a fuse element 343a which serves as a program element, an N-channel MOS transistor 341a, and an inverter 342a. Fuse element 343a and N-channel MOS transistor 341a are connected in series between power supply voltage VCC and ground voltage GND through a connection node Nh, and the gate of N-channel MOS transistor 341a is connected to node N4. In addition, inverter 342a inverts the signal transmitted to connection node Nh and transmits the inverted signal to the gate of P-channel MOS transistor 358.
Fuse element 343a is blown in response to the incidence of a laser beam applied from the outside of the memory and the state of fuse element 343a changes from a conductive state to a nonconductive state. As a result, tuning unit 344a changes the state of P-channel MOS transistor 358 from a conductive state to a nonconductive state when the fuse is blown. The same thing is true for remaining tuning units 344b to 344d. 
Referring back to FIG. 9, a case where the channel resistance ratio of P-channel MOS transistors 352 to 355 is, for example, 1:2:4:8, will be considered.
In an initial state, transistor switches 358 to 360 are conductive and transistor switch 361 is nonconductive. Accordingly, P-channel MOS transistor 355 functions as a resistance element.
In this state, combined channel resistance Rc can be adjusted and constant voltage Vn6 can be raised or lowered in accordance with the tuning of tuning circuit 340 based on a predetermined combination of tuning units. It is, therefore, possible to correct the deviation of a target level which has been set in a design phase by conducting tuning to thereby blow fuse elements after designing the memory.
For example, in tuning circuit 340, if fuse element 343a is blown, P-channel MOS transistor 358 becomes nonconductive and P-channel MOS transistor 352 functions as a resistance element. As a result, combined channel resistance Rc increases and constant current Vn6 rises. Accordingly, the voltage level of the reference voltage in an initial phase is corrected to follow the target level of the reference voltage by tuning.
Reference voltage generation circuit 300a also includes an N-channel MOS transistor 301 and a DQM terminal as an external terminal, both of which are used during a test.
N-channel MOS transistor 301 is connected between DQM terminal and node N0 and the gate thereof receives a test mode signal TM which is activated to xe2x80x9cHxe2x80x9d level during a test. Namely, during a test, by inputting test mode signal TM, N-channel MOS transistor 301 can be turned into a conductive state and reference voltage REF1 can be inputted into transistor 301 directly from the outside of the memory using DQM terminal.
By adopting such a configuration, it is possible to directly input the reference voltage from the outside during a test, so that the internal voltage can be set at arbitrary level and a screening test can be easily executed. Further, the setting of the internal voltage during the test can be facilitated.
Nevertheless, as shown in three types of internal voltages V1 to V3 in FIG. 8, a semiconductor memory device is provided with a plurality of levels of internal voltages to correspond to various internal circuits, respectively. Therefore, it is necessary to provide many DQM terminals to input the reference voltage (REF1 in FIG. 9) so as to conduct a screening test in the configuration shown in FIGS. 9 and 10.
As already described, since it is necessary to fixedly input a constant voltage for a test into each DQM terminals as an external terminal, the DQM terminal cannot be used to input/output the other test signals. Because of the limited number of terminals, therefore, it is difficult to minutely adjust all the internal voltages during a test based on the configuration shown in FIG. 9.
Furthermore, since such a screening test is intended to accelerate the defect of an internal circuit, it is considered to suffice that the internal voltage can be slightly raised or lowered from the reference voltage which is set.
The present invention provides a semiconductor memory device capable of performing a screening test to internal circuits without directly inputting reference voltages from an outside of the semiconductor memory device and without increasing the number of external terminals during the test.
According to one aspect of the present invention, a semiconductor memory device includes: an internal voltage generation circuit; a reference voltage generation circuit; a plurality of signal terminals; and a reference voltage change indication circuit.
The internal voltage generation circuit controls an internal voltage supplied to an internal circuit in accordance with a reference voltage. The reference voltage generation circuit generates the reference voltage. The plurality of signal terminals transmit and receive a signal to and from an outside of the semiconductor memory device.
During a test, the reference voltage change indication circuit indicates a change of the reference voltage on the basis of a binary input signal to each of the signal terminals with respect to the reference voltage generation circuit.
Therefore, a main advantage of the present invention is to indicate a change of a reference voltage on the basis of a binary input signal to signal terminals during a test. Accordingly, it is possible to adjust an internal voltage without necessity for directly setting a level of a reference voltage with test dedicated external terminals and without increasing the number of the external terminals to efficiently perform a screening test.